In recent years, with the spread of small-sized portable telephones, mobile communications utilizing analog or digital modulation systems have been developed. In a small-sized portable telephone, a reduction in chip size and an increase in integration density of functional elements are very important.
Especially, a GaAs IC chip, i.e., an IC chip employing a GaAs substrate, used in an RF front end part is backward in integration compared with IC chips used in other parts. So, an increase in the integration density of the GaAs IC chip and a reduction in the chip size have been strongly demanded.
FIG. 13 is a block diagram schematically illustrating a structure of an RF front end part of a conventional portable telephone. In the figure, reference numerals 8a and 8b designate mixers, i.e., frequency changers (hereinafter referred to as MIX), numeral 1 designates a variable attenuator for transmission (hereinafter referred to as TX-ATT), numeral 6 designates a variable attenuator for reception (hereinafter referred to as RX-ATT), numeral 2 designates a power amplifier (hereinafter referred to as PA) using a GaAs field effect transistor (hereinafter referred to as FET), numeral 3a designates a band pass filter (hereinafter referred to as BPF), and numeral 4 designates a single pole double throw switch (hereinafter referred to as SPDT-SW). The SPDT-SW 4 has three terminals, and a signal input to one of the three terminals is selectively output from the remaining two terminals. Reference numeral 7 designates a low noise amplifier for reception (hereinafter referred to as LNA). Reference numeral 9 designates a negative voltage generator (hereinafter referred to as NVG) for supplying a negative voltage V.sub.GB to the PA 2 because the
2 comprising a GaAs FET needs a negative gate bias voltage. Reference numeral 10 designates a control logic circuit for controlling the TX-ATT 1, the RX-ATT 6, and the SPDT-SW 4 in response to a control signal CONT. Since a single power supply voltage V.sub.DD is used in this portable telephone, for a control signal output from the control logic circuit 10, the power supply voltage V.sub.DD is used as a high potential (hereinafter referred to as "H") and a ground voltage (hereinafter referred to as GND), i.e., 0V, is used as a low potential (hereinafter referred to as "L"). Reference numeral 11 designates a transmitted RF signal input port (hereinafter referred to as TX-IN), and numeral 14 designates a received RF signal output port (hereinafter referred to as RX-OUT). Reference numeral 5 designates an antenna port (hereinafter referred to as ANT), that is, an I/O port connected to an antenna 5a. Reference numeral 12 designates a V.sub.NVG input port (hereinafter referred to as V.sub.NVG -IN) receiving a signal V.sub.NVG which controls an output voltage from the NVG 9. The power supply voltage V.sub.DD is used as V.sub.NVG. Reference numeral 13 designates a control signal input port (hereinafter referred to as CONT-IN) receiving the control signal CONT which controls the operation of the control logic circuit 10. The control logic circuit 10 is a part of a base band IC comprising Si (not shown), and it is controlled by a control signal CONT that is output from a circuit in the base band IC other than the control logic circuit 10.
A description is given of the operation. The SPDT-SW 4 connects the ANT 5 to the TX-IN 11 during reception and connects the ANT 5 to the RX-OUT 14 during transmission, and the control circuit 10 controls the switching of the SPDT-SW 4 and controls the TX-ATT 1 and the RX-ATT 6. Further, during transmission, the NVG 9 generates a negative voltage V.sub.GB from a positive power supply voltage applied thereto and supplies the negative voltage V.sub.GB to the PA 2 as a gate bias voltage.
During transmission, an RF signal input to the TX-IN 11 is subjected to frequency conversion by the MIX 8a, and the frequency converted signal is input to the TX-ATT 1. In the TX-ATT 1, the signal is attenuated, as desired, in response to the power of the input signal. Then, the attenuated signal is amplified by the PA 2, and unnecessary frequency components are eliminated from the attenuated signal by the BPF 3a. Thereafter, the signal is transmitted through the SPDT-SW 4 and ANT 5 and output from the antenna 5a.
During reception, an RF signal received by the antenna 5a is transmitted through the ANT 5 and the SPDT-SW 4 to the RX-ATT 6. In the RX-ATT 6, it is attenuated, as desired, in response to the power of the input signal. Then, unnecessary frequency components are eliminated from the attenuated signal by the BPF 3b. Thereafter, the signal is amplified by the LNA 7 and subjected to frequency conversion by the MIX 8b. Finally, it is taken out from the RX-OUT 14.
In the circuit shown in FIG. 13, the MIXs 8a and 8b, the TX-ATT 1, the PA 2, the SPDT-SW 4, the RX-ATT 6, and the LNA 7 are integrated on a single GaAs substrate (not shown). However, the NVG 9 and the control logic circuit 10 are located outside the GaAs substrate. For example, the NVG 9 is constituted by an IC comprising an Si substrate for the IC only, and the control logic circuit 10 is constituted by a base band IC comprising an Si substrate. Therefore, the number of parts of the transceiver IC is increased, so that the fabrication process is complicated. Further, it is difficult to reduce the size of the transceiver IC.
In order to solve the above-described problems, it might be thought that all the constituents of the circuit, i.e., the MIXs 8a and 8b, the TX-ATT 1, the PA 2, the LNA 7, the SPDT-SW 4, the RX-ATT 6, the NVG 9, and the control logic circuit 10 might be integrated on a single GaAs substrate, and a switch and an attenuator having simple structures are employed. However, the integration of these constituents on a single substrate and the use of a simple switch and a simple attenuator adversely affect the transmission and reception characteristics of the switch and the attenuator as described hereinafter.
FIG. 14 is a circuit diagram illustrating a serial-parallel switch generally used as an SPDT switch in a circuit as shown in FIG. 13. In the figure, reference numerals 51, 52, 53, and 54 designate depletion type field effect transistors (hereinafter referred to as D-FETs), numerals 55, 56, 57, 58, 59, and 60 designate resistors having high resistances for bias application, numeral 61 designates a capacitor for grounding source electrodes of the FETs 52 and 54 for AC, and an end of the capacitor 61 is grounded. Reference numeral 62 designates a transmission side input port (hereinafter referred to as SW-TX), numeral 63 designates a reception side output port (hereinafter referred to as SW-RX), numeral 5 designates an antenna port, and numerals 64 and 65 designate control signal input ports. The control signal input ports 64 and 65 are connected to the control logic circuit 10 shown in FIG. 13 and receive control signals from the control logic circuit 10. The control signal input to the control signal input port 64 is an inverted signal, i.e., a signal opposite to the control signal input to the control signal input port 65. For the control signal, as described above, the power supply voltage V.sub.DD is used as "H" and the ground voltage, i.e., 0V, is used as "L". Reference numeral 66 designates a supply voltage port for raising potentials of transmission lines, i.e., potentials of sources and drains of the transistors 51 and 53, to operate the transistors 51 and 53, in response to the power supply voltage V.sub.DD and the ground voltage applied to the control signal input ports 64 and 65.
A description is given of the operation. During transmission, "H" (.apprxeq.V.sub.DD) is applied to the control signal input port 64 while "L" (.apprxeq.0V) is applied to the control signal input port 65, whereby the FETs 52 and 53 are turned on and the FETs 51 and 54 are turned off, and an RF signal input to the SW-TX 62 is output from the ANT 5. At this time, since the FET 51 is in the OFF state, no RF signal is output from the SW-RX 63. Even when the signal leaks from the FET 51, the leakage signal is reflected because the FET 52 is in the ON state, and leakage of a signal from the SW-RX 63 is suppressed.
At the reception, "H" (.apprxeq.V.sub.DD) is applied to the control signal input port 65 while "L" (.apprxeq.0V) is applied to the control signal input port 64, whereby the FETs 51 and 54 are turned on and the FETs 52 and 53 are turned off, and an RF signal input to the antenna port 5 is output from the reception side RF signal output port 63. At this time, since the FET 53 is in the OFF state, no RF signal is output from the SW-TX 62. Even when the signal leaks from the FET 53, the leakage signal is reflected because the FET 54 is in the ON state, and leakage of a signal from the SW-TX 62 is suppressed.
The serial-parallel SPDT switch shown in FIG. 14 has the advantage of reduced insertion loss and high isolation. Recently, an SPDT switch that can treat a high output voltage at transmission ranging from 24 dBm to 30 dBm, at a low operating voltage, for example, a control voltage of 3/0 V or 0/-3 V, has been realized by using an FET having two different pinch-off voltages or a dual gate FET. Such an SPDT switch is reported in "3V Single Bias Operating SPDT T/R MMIC Switches for PHP Using the Symmetrical MESFETs", TECHNICAL REPORT OF THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, No. MW93-157 (February, 1994) or in "A 3V MMIC Chip Set for 1.9 GHz Mobile Communication Systems", 1995 IEEE International Solid-State Circuits Conference.
However, since a serial-parallel SPDT switch as disclosed in these publications is usually as large as 1.times.1 mm, when the serial-parallel SPDT switch is used in an IC, the chip size of the IC is unfavorably increased.
Furthermore, in order to realize a single power supply operation between V.sub.DD and GND (0V), it is necessary to make the circuit open for DC and shorted for AC using the capacitor 61. For this purpose, however, a capacitance over ten pF is required for GHz band operation, and an element having such a high capacitance is large in size, resulting in an unwanted increase in the chip size.
FIG. 12 is a circuit diagram illustrating an SPDT switch that can solve the problems mentioned above. This SPDT switch has a relatively simple structure, i.e., the number of FETs is reduced to two and no capacitor is included, thereby to reduce the size of an IC chip including this SPDT switch. In the figure, the same reference numerals as those shown in FIG. 10 designate the same or corresponding parts. Reference numeral 4a designates an SPDT switch, numerals 70 and 71 designate D-FETs, numerals 72, 73, 74, and 75 designate resistors for bias application, and numeral 76 designates a resistor for raising potentials of transmission lines, i.e., potentials of sources and drains of the transistors 51 and 53, in response to the power supply voltage V.sub.DD.
A description is given of the operation. During transmission, "H" (.apprxeq.V.sub.DD) is applied to the control signal input port 64 and "L" (.apprxeq.0V) is applied to the control signal input port 65, whereby the FET 70 is turned on and the FET 71 is turned off, and an RF signal input to the SW-TX 62 is output from the antenna port 5. Since the FET 71 is in the OFF state, no RF signal is output from the SX-RX 63.
During reception, "H" (.apprxeq.V.sub.DD) is applied to the control signal input port 65 and "L" (.apprxeq.0V) is applied to the control signal input port 64, whereby the FET 71 is turned on and the FET 70 is turned off, and an RF signal input to the antenna port 5 is output from the SW-RX 63. Since the FET 70 is in the OFF state, no RF signal is output from the SW-TX 62.
Although an SPDT switch having such a simple structure as shown in FIG. 12 has the advantage of reducing the chip size, it has the following drawbacks.
The SPDT switch 4a shown in FIG. 12 is in the transmitting state when the FET 70 is in the ON state and the FET 71 is in the OFF state. In the transmitting mode of the SPDT switch 4a, when the gate to source voltage (gate to drain voltage) of the FET 71 is low, the OFF state of the FET 71 is not sufficient, and the pinch-off state of the FET 71 is not maintained against a high power. Thereby, signals leak at the SW-RX 63 with an increase in the power of signals input to the SW-TX 62. In recent years, a portable transceiver using a single power supply of about 3V is popular. However, when such a low power supply voltage is used, since the voltage for raising potentials of transmission lines, i.e., V.sub.DD, is equal to 3V, a difference between the gate voltage and the source voltage (drain voltage) of the FET 71 in the OFF state is as small as -3V (=GND (0V)-V.sub.DD (3V)). In this case, it is impossible to sufficiently prevent signals from leaking at the SW-RX 63 when the power of signals input to the SW-TX 62 is high. As a result, insertion loss of the SPDT switch 4a is increased, and isolation between the SPDT switch 4a and the RX-ATT 6 is degraded.
As described above, in the prior art IC equipped with a simple SPDT switch for reducing the chip size and operated with a single power supply, since the power supply voltage V.sub.DD is used as a high potential "H" and the ground voltage (=0V) is used as a low potential "L", when it is operated with a power supply voltage as low as 3V or with a control signal of 0V, insertion loss of the SPDT switch is increased and isolation between the SPDT switch and the RX-ATT 6 is degraded when the transmission power is high.